This invention relates to large scale semiconductor arrays and, more particularly, to aligning a plurality of integrated circuit semiconductor chips into a linear or two-dimensional array.
There is a growing need for an inexpensive and simple method for abutting or aligning semiconductor integrated circuit (IC) chips and interconnecting them to effectively product page width linear arrays or two-dimensional arrays extending up to a full page size. There is a demand for large area arrays for various applications such as displays, read or write image bars, and thermal ink jet printers. Conventionally, a plurality of IC chips are formed from a wafer die and are separated from each other by a dicing technique. The chips are then tested and the "good" chips are bonded together to form a larger array. The dicing technique creates fractures along the etched crystal plane leaving edges and sometimes damaging passivation layers on the circuit surface near the fracture. A further problem with prior art dicing techniques is that chips to be aligned are not the same height, and a slight lateral mis-alignment results since the aligned surface are at an angle to each other. Chip mis-alignment can result from wafer-to-wafer variations.
The present invention is directed towards forming large area arrays by butting together a plurality of integrated circuit chips using techniques avoiding the above-mentioned problems and not disclosed in the prior art. According to one aspect of the invention, the wafer fabrication technique is modified to include a combination of orientation dependent etching and reactive ion etching steps to enable chip separation to be accomplished without the resulting chip edges or surface damage. More particularly, the invention is directed towards a method for separating integrated circuit chips formed on a crystalline substrate comprising the steps of
(a) forming a plurality of vertical trenches along predetermined intersecting lateral boundaries on the top surface of said substrate by a reactive ion etch process,
(b) filling in said trenches with an etchable material,
(c) forming a plurality of integrated circuits on the surface of said substrate with said lateral boundaries,
(d) passivating both surfaces of said substrate,
(e) and orientation etching a plurality of V-shaped grooves on the back of the wafer in general alignment with said vertical trenches, said etching being adapted to etch into, and form new trenches from said etchable material,
whereby said integrated circuits are separated by the combined action of said top and bottom etching steps, said circuits being formed with planar butting surfaces created by the vertical trench formation.
The following publications are considered as material: U.S. Pat. No. 4,612,554 to Poleshuk, discloses an ink jet printhead apparatus comprising two identical parts and a method for producing the same. A plurality of V-shaped groves are anisotropically etched on each part of the apparatus between a linear array of heating elements. The grooves allow the structures to be mated in an automatically self-aligned manner.
U.S. Pat. No. 4,604,161 to Araghi teaches a method for fabricating an image sensor array. An active surface of an array chip is etched to form a V-shaped groove which marks an array end. A groove is then cut into the opposite inactive surface with a centerline parallel to, but offset form, the centerline of the V-shaped groove. Forcible fracturing of the chip along the {111} crystalline plane between the grooves produces a straight array end for butting against the end of a like array.
Japanese Pat. No. 60-157236 to Murata discloses a method of dicing a semiconductor substrate. A first full-cut or half-cut is made into one side of the semiconductor substrate with a first blade. Then, another cut is made into the other side of the semiconductor substrate, opposite the first cut, with a blade wider than the first blade.
U.S. Pat. No. 4,589,952 to Behringer et al discloses a method of making trenches having substantially vertical sidewalls in a silicon substrate, wherein a thick photoresist layer, a silicon nitride layer and a thin photoresist layer are sequentially formed on the surface of the substrate and reactive ion etched to form the trenches.
U.S. Pat. No. 4,542,397 to Biegelsen et al discloses the formation of large scale arrays from integrated chips on a wafer, which is characterized as having a parallelogrammatic like geometry.